1. Field of the Invention
The present invention generally relates to a charged device model (CDM) electrostatic discharge (ESD) protection for integrated circuits (ICs). More specifically, the present invention relates to a CDM ESD protection circuit for use in a metal oxide semiconductor (MOS) circuit or input/output (I/O) circuit.
2. Description of the Related Art
U.S. Pat. No. 5,901,022 to Ker (hereinafter ""022 patent) and U.S. Pat. No. 5,729,419 to Lien (hereinafter ""419 patent) disclose two ways of providing CDM ESD protection to CMOS ICs. FIG.1 shows one type of conventional ESD protection for CDM ESD event as taught by ""022 patent, and FIG. 2 shows another type of conventional ESD protection for CDM ESD event as taught by the ""419 patent. In FIG. 1, there is an inductor 102 placed between an input pad 104 and a gate oxide of the first input stage 106 to limit the CDM ESD current discharging through the gate oxide of the first input stage 106. In FIG.2, the CDM ESD clamps 310 and 311 are added between an output pad 301 and output nodes 321 and 322 of the pre-driver circuits 306 and 307 to clamp the overstress voltage across the gate oxide of the output transistors 302 and 303.
The circuit diagram to realize the conventional ESD protection for CDM ESD event shown in FIG. 2 is illustrated in FIG.3, noting that the output nodes 321 and 322 of the pre-driver inverters 306 and 307 are connected to the CDM clamps 310 and 311. The CDM ESD current discharging paths during the CDM ESD event in this conventional art are schematically drawn in FIG.4 by dashed lines with arrows.
Generally, the common substrate of a CMOS chip has a thickness of 500 to 600 xcexcm, which is much thicker than that of the N-well or P-well regions in general CMOS technologies. Accordingly, the CDM charges are mainly stored in among the large-volume common p-type substrate. During a CDM ESD event, the output pad is grounded, and the CDM charges are discharged through the devices of the CMOS circuits to the grounded output pad. The CDM ESD discharging current has a very fast transition. For a typical 1000 V CDM event, the CDM discharging current can be as high as 15 amps (A) with a rise time of 0.5 to 1 nanoseconds (ns). Under such fast CDM transition, the CDM charges are often discharged through the path that has the lowest impedance along the CMOS circuits. In FIG. 4, the CDM charges (hereinafter CDM Q) which are originally stored in the substrate, is schematically illustrated in the circuit at the bulk (substrate) of Mnd2 of the pre-driver inverter. When the output pad is grounded, the CDM Q is discharged through three possible current paths, marked as ICDM_1, ICDM_2 and ICDM_3 in FIG. 4.
As discussed in the ""419 patent, the CDM discharging current path should be the ICDM_2 in FIG.4. Along the path of ICDM_2, the CDM current goes from the p-type substrate into the bulk of Mnd2, and then through the parasitic drain-to-bulk diode (Dn2) of Mnd2 device to the drain of Mnd2 (the output node of pre-driver inverter). Then, the CDM current is discharged through the added CDM clamp to the grounded output pad. However, if the CDM Q stored in the common substrate have a negative polarity, then the diode Dn2 has to be broken down to bypass the CDM Q from the p-type substrate to the output node of the pre-driver inverter. In this instance, the diode Dn2 cannot be broken down to conduct the fast CDM Q in a time period of approximately 1 ns. Moreover, the breakdown voltage across the diode Dn2 and the voltage drop across the added CDM clamp cause a high voltage drop from the common p-type substrate to the grounded output pad, which in turn cause the path of ICDM_2 in FIG.4 to have a high impedance due to the CDM fast-transition current.
The path of ICDM_3 in FIG. 4 goes from the p-type substrate to the N-well of PMOS (Mpd2), through Dnw2 or through in turn Dn2 and Dp2, and then to the output PMOS Mpo1 through the VDD power line. If the CDM Q stored in the p-type substrate have a negative polarity, then the diode Dnw2 (n-well/p-type substrate junction), which has a high breakdown voltage of 20xcx9c30 V, has to be broken down to conduct the CDM Q into the n-well region of the PMOS Mpd2. With such high n-well p-type substrate breakdown voltage, the path of ICDM_3 equivalently has a high impedance for the CDM Q. Therefore, the CDM Q is seldom discharged through the this path ICDM_3.
Because the diode breakdown of the diode Dn2 or Dnw2 causes a delay in time and a high-impedance response along the path, negative CDM Q stored in the p-type substrate cannot be efficiently discharges through the paths of ICDM_2 or ICDM_3. The negative CDM Q stored in the p-type substrate are therefore discharged through the path of ICDM_1 as shown in FIG. 4. The discharging path of ICDM_1 is formed directly from the p-type substrate through the output NMOS Mno1 to the grounded output pad, even if there is a CDM clamp added between the output node of pre-driver inverter and output pad. This means that the added CDM clamp in FIG. 4 has not provided the desired CDM ESD discharging path to protect the output NMOS transistors. This is a defective design that does not sufficiently protect the output buffer against the CDM ESD events.
To more clearly described the CDM discharging path in FIG.4, a cross-sectional view of the partial devices (Mno1, Mnd2 and Mpd2) in the circuits shown in FIG.4 is illustrated in FIG. 5. As seen in FIG.5, the CDM clamp is connected from the drain of Mpd2 and Mnd2 (the output node of the pre-driver inverter) to the output pad. The parasitic diodes (Dn2 in Mnd2, Dp2 in Mpd2, Dnw2 in Mpd2, and Dn1 in Mno1) are indicated in FIG.5 by the symbol of diode. The case of negative CDM Q stored in the common p-type substrate is drawn in FIG. 6 to clearly describe the real CDM current discharging path in the output circuits. The possible CDM ESD discharging paths are marked as ICDM_1, ICDM_2, and ICDM_3, which are corresponding to the paths as shown in FIG. 4. In FIG. 6, the fastest discharging path to discharge the negative CDM Q stored in the common p-type substrate is the path ICDM_1. The discharging paths of ICDM_2 and ICDM_3 are also drawn in FIG. 6, to physically show these inefficient discharging paths. Thus, the added CDM clamp in the ""410 patent does not improve the CDM ESD level of the output buffer. The CDM Q is still mainly discharged through the output buffer itself.
Although the CDM ESD design in the conventional art is defective and inefficient, it has shown at least that the CDM ESD protection has been a serious concern in the deep sub-micron CMOS IC with much thinner gate oxide.
Accordingly, an object of the present invention is provided a more efficient CDM ESD protection circuit to output circuits, input circuits, high/low voltage tolerant I/O circuits, and isolated N-well and P-well biased CMOS circuits to which one or more CDM clamps are directly connected to one or more bulks of the MOS transistors.
It is another object of the present invention to provide, in addition to the CDM clamps, one or more bi-directional diode strings between the power lines to improve the CDM ESD level of the integrated circuit.
In accordance with the present invention, an output CDM ESD protection circuit is provided for use in an integrated circuit. In particular, the output circuit includes an output pad, VDD and VSS power lines, one or more MOS transistors disposed between the output pad and the VDD or VSS power line, one or more MOS circuits with CMOS transistors disposed between the VDD and VSS power lines, and one or more CDM ESD protection circuits disposed between the output pad and the MOS circuits, wherein the drains of the CMOS transistors are directly coupled to the respective gates of the MOS transistors, and the CDM ESD protection circuits are directly coupled to the respective bulks of the CMOS transistors.
In accordance with another aspect of the present invention, an input CDM ESD protection circuit is provided for the integrated circuit in which the input circuit includes an input pad and one or more bi-directional diode strings disposed between power lines, wherein one or more CDM ESD protection circuits are disposed between the input pad and MOS transistors, and directly coupled to the respective bulks of the MOS transistors.
In accordance with yet another aspect of the present invention, an analog circuit with different input stage is provided for the integrated circuit. In particular, the analog circuit includes an input pad, a HBM/MM ESD protection circuit coupled to the input pad and disposed between VDD_I/O and VSS_I/O power lines, a pair of bi-directional diode strings respectively disposed between the VDD_I/O power line and either VDDA or VSSA power line, CMOS transistors disposed between the VDDA and VSSA power lines, and a CDM ESD protection circuit disposed between the HBM/MM ESD protection circuit and one of the CMOS transistors, wherein the CDM ESD protection circuit is directly coupled to a bulk of one of the CMOS transistors.
In accordance with still another aspect of the present invention, a high-voltage tolerant I/O circuit is provided for use in the integrated circuit. The I/O circuit includes an I/O pad, CMOS transistors disposed between power lines, and a CDM ESD protection circuit disposed between the I/O pad and the CMOS transistors, wherein the CDM ESD protection circuit is directly coupled to a bulk of one of the CMOS transistors.
Related aspects and advantages of the invention will become apparent and more readily appreciated from the following detailed description of the invention, taken in conjunction with the accompanying drawings.